1. Technical Field
The present disclosure generally relates to techniques for preparing electronic samples that may be used in, e.g., failure analysis of electronic devices such as semiconductor dies, chips, integrated circuits, packages, boards, and the like. More particularly, and not by way of any limitation, the present disclosure is directed to an apparatus and method for electronic sample preparation using temperature-controlled stress reduction.
2. Description of Related Art
Sample preparation is often required in the field of semiconductor failure analysis. For example, backside thinning and polishing may be necessary for validation techniques such as Focused Ion Beam (FIB) circuit editing and optical probing using Photon Emission or Laser stimulus methods. Conventional sample preparation techniques continue to encounter various challenges, however, especially as new packages involving ever larger semiconductor dies with are being introduced. Methods such as flat lapping are typically relegated to “time and look” procedures that allow no way to interactively check the endpoints of preparation in a sample semiconductor die. In addition, the issue of die breakage or cracking during sample preparation has also become significant.